1. Field of the Invention
The present invention relates to integrated circuit design tools. In particular, the present invention relates to integrated circuit design tools hat optimize area performance and signal integrity in integrated circuits.
2. Discussion of the Related Art
The interconnection wiring ("interconnect") among circuit elements in an integrated circuit is expected to dominate signal delays and to limit achievable circuit density of an integrated circuit. Existing design methods, which treat interconnect as "parasitics" and focus on optimizing transistors and logic gates, are ill-equipped to provide a design that delivers the necessary performance. Typically, in a conventional design method, the circuit elements of an integrated circuit are first synthesized and placed. A global routing tool is then used to interconnect these circuit elements. Due to the interconnect dominance, accurate estimation of performance is available only after global routing. Because placement and routing are performed relatively independently, even though some tools take into consideration the connectivity among circuit elements in providing the placement, the global routing tool's ability to address power, timing, and congestion issues is severely limited.
Various techniques have been applied to address signal propagation performance in an integrated circuit design. For example, U.S. Pat. No. 5,638,291, entitled "Method and Apparatus for Making Integrated Circuits by Inserting Buffers into a Netlist to Control Clock Skew" to Li et al., discloses modification of a net list to insert buffers into clock signal paths to control clock skew. As another example, U.S. Pat. No. 5,396,435, entitled "Automated Circuit Design System and Method for Reducing Critical Path Delay Times" to Ginetti, discloses modification to a logic circuit to reduce delays in a critical path of an integrated circuit. However, the effectiveness of these methods for increasing circuit performance is constrained by their inability to concurrently affect placement of circuit elements.
Concurrent placement and wiring routing is disclosed in U.S. Pat. No. 4,593,363, entitled "Simultaneous Placement and Wiring for VLSI Chips" to Burstein et al. The '363 patent discloses an iterative method in which a global router is invoked to route networks redistributed under a hierarchical placement algorithm.